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Data Sheet No.PD94253
IRU3048
DUAL SYNCHRONOUS PWM CONTROLLER CIRCUITRY AND LDO CONTROLLER
PRELIMINARY DATA SHEET
FEATURES
Dual Synchronous Controller in 16-Pin Package with 1808 out-of-phase operation LDO Controller with 40mA drive Configured as 2-Independent PWM Controller Flexible, Same or Separate Supply Operation Operation from 4V to 25V Input Internal 200KHz Oscillator Soft-Start controls all outputs Fixed Frequency Voltage Mode 500mA Peak Output Drive Capability Programmable Outputs
DESCRIPTION
The IRU3048 IC combines a Dual synchronous Buck controller and a linear regulator controller, providing a cost-effective, high performance and flexible solution for multi-output applications. The Dual synchronous controller is configured as 2-independent PWM controller. IRU3048 provides a separate adjustable output by driving a switch as a linear regulator. This device features an internal 200KHz oscillator, under-voltage lockout for all input supplies, an external programmable soft start function as well as output under-voltage detection that latches off the device when an output short is detected.
APPLICATIONS
DDR Memory Source Sink Vtt Application Graphic Card Hard Disk Drive Power supplies requiring multiple outputs
TYPICAL APPLICATION
12V 5V
VcH1 Vcc 3.3V C1 R1 VOUT3 C2 R2 C3 R3 Comp1 R4 Comp2 Fb3
VcH2 HDrv1 Q2 L1 VOUT1
Q1 VOUT3
LDrv1
Q3
C6
U1 IRU3048
PGnd R5 Fb1 Fb2 HDrv2 Q4 L2 VOUT2 LDrv2 Q5 R7 C7
R6
C4
SS C5
Gnd
R8
Figure 1 - Typical application of IRU3048 configured as 2-independent converter.
PACKAGE ORDER INFORMATION
TA (C) 0 To 70 0 To 70
Rev. 1.7 09/12/02
DEVICE IRU3048CF IRU3048CS www.irf.com
PACKAGE 16-Pin TSSOP (F) 16-Pin SOIC NB (S)
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IRU3048
ABSOLUTE MAXIMUM RATINGS
Vcc Supply Voltage .................................................. VcH1=VcH2 Supply Voltage ...................................... Storage Temperature Range ...................................... Operating Junction Temperature Range ..................... 25V 30V (not rated for inductive load) -65C To 150C 0C To 125C
PACKAGE INFORMATION
16-PIN PLASTIC TSSOP (F)
TOP VIEW
16-PIN PLASTIC SOIC NB (S)
TOP VIEW
Gnd 1 Fb2 2 Comp1 3 Comp2 4 VcH2 5 HDrv2 6 LDrv2 7 PGnd 8
16 Fb1 15 SS 14 Fb3 13 VOUT3 12 VcH1 11 HDrv1 10 LDrv1 9 Vcc
Gnd 1 Fb2 2 Comp1 3 Comp2 4 VcH2 5 HDrv2 6 LDrv2 7 PGnd 8
16 Fb1 15 SS 14 Fb3 13 VOUT3 12 VcH1 11 HDrv1 10 LDrv1 9 Vcc
uJA=908C/W
uJA=858C/W
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over Vcc=5V, VcH1=VcH2=12V, T A=0 to 70C. Typical values refer to TA=25C. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient temperature. PARAMETER Reference Voltage Fb Voltage Fb Voltage Line Regulation UVLO UVLO Threshold - Vcc UVLO Hysteresis - Vcc UVLO Threshold - VcH1 UVLO Hysteresis - VcH1 UVLO Threshold - VcH2 UVLO Hysteresis - VcH2 UVLO Threshold - Fb UVLO Hysteresis - Fb Supply Current Vcc Dynamic Supply Current VcH1 Dynamic Supply Current VcH2 Dynamic Supply Current Vcc Static Supply Current VcH1 Static Supply Current VcH2 Static Supply Current Soft-Start Section Charge Current SYM VFB LREG TEST CONDITION MIN 1.225 5UVLOVCC Supply Ramping Up UVLOVCH1 Supply Ramping Up UVLOVCH2 Supply Ramping Up UVLOFB Fb Ramping Down
Dyn ICC Dyn ICH1 Dyn ICH2 ICCQ ICH1Q ICH2Q SSIB
Freq=200KHz, CL=1500pF Freq=200KHz, CL=1500pF Freq=200KHz, CL=1500pF SS=0V SS=0V SS=0V SS=0V
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PARAMETER Error Amp Fb Voltage Input Bias Current Fb Voltage Input Bias Current Transconductance 1 Transconductance 2 Oscillator Frequency Ramp Amplitude Output Drivers Rise Time Fall Time Dead Band Time Max Duty Cycle Min Duty Cycle LDO Controller Drive Current Fb Voltage Input Bias Current SYM IFB1 IFB2 gm1 gm2 Freq VRAMP Tr Tf TDB TON TOFF ILDO VFBLDO ILDO(BIAS) CL=1500pF CL=1500pF Fb=1V, Freq=200KHz Fb=1.5V 50 85 0 30 1.225 TEST CONDITION SS=3V SS=0V MIN TYP -0.1 -64 400 600 180 200 1.25 35 50 150 90 0 45 1.25 0.5 220 MAX UNITS mA mA mmho mmho KHz VPP ns ns ns % % mA V mA
100 100 250
1.275 2
PIN DESCRIPTIONS
PIN# 1 2 16 PIN SYMBOL Gnd Fb2 Fb1 PIN DESCRIPTION Ground pin. Inverting inputs to the error amplifiers. These pins work as feedback inputs for each channel, and are connected directly to the output of the switching regulator via a resistor divider to set the output voltages. Compensation pins for the error amplifiers. Supply voltage for the high side output drivers. These are connected to voltages that must be at least 4V higher than their bus voltages (assuming 5V threshold MOSFET). A minimum of 1mF high frequency capacitor must be connected from these pins to PGnd pin to provide peak drive current capability. Output driver for the high side power MOSFET. Connect a diode, such as BAT54 or 1N4148, from these pins to ground for the application when the inductor current goes negative (Source/Sink), soft-start at no load and for the fast load transient from full load to no load. Output driver for the synchronous power MOSFET. This pin serves as the separate ground for MOSFET's driver and should be connected to the system's ground plane. Supply voltage for the internal blocks of the IC. Driver signal for the LDO's external transistor. LDO's feedback pin, connected to a resistor divider to set the output voltage of LDO. Soft-Start pin. The converter can be shutdown by pulling this pin below 0.5V.
3 4 5 12
Comp1 Comp2 VcH2 VcH1
6 11
HDrv2 HDrv1
7 10 8 9 13 14 15
LDrv2 LDrv1 PGnd Vcc VOUT3 Fb3 SS
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IRU3048
BLOCK DIAGRAM
Vcc 9
Bias Generator 64uA Max 4.2V / 4.0V UVLO PR O 3V 1.25V
12 V c H 1
25uA
11 HDrv1
SS 15
VH c1 VH c2
3.5V / 3.3V 3.5V / 3.3V
PR O PWM Comp1 Error Amp1 25K 1.25V 25K
10 LDrv1 R Q S
Reset Dom
Fb1 16
Comp1
3
Ramp1 Two Phase Oscillator Ramp2
Set1 SS > 2V
5 VcH2
6
Set2
HDrv2
S
PWM Comp2 Error Amp2 25K 1.25V 25K
Q R
Reset Dom
7 LDrv2
Fb2
2
0.5V
8 PGnd
PR O
Comp2
4
Vcc 25K 1.25V 2V 25K
Fb3 14
SS 40mA LDO Controller
Gnd
1
13 VOUT3
Figure 2 - Block diagram of the IRU3048.
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THEORY OF OPERATION
Introduction The IRU3048 is designed for multi-outputs applications. It includes two synchronous buck controllers and a linear regulator controller. The two synchronous controller operates with fixed frequency voltage mode and is configured as two independent controllers. The timing of the IC is provided through an internal oscillator circuit. These are two out of phase oscillators. Soft-Start The IRU3048 has a programmable soft start to control the output voltage rise and limit the current surge at the start-up. To ensure correct start-up, the soft-start sequence initiates when the Vcc, VcH1 and VcH2 rise above their threshold and generates the Power On Reset (POR) signal. Soft-start function operates by sourcing an internal current to charge an external capacitor to about 3V. Initially, the soft-start function clamps the E/ A's output of the PWM converter. As the charging voltage of the external capacitor ramps up, the PWM signals increase from zero to the point the feedback loop takes control. Out of Phase Operation The IRU3048 drives its two output stages 1808 out of phase. In application with single input voltage, the out of phase operation reduces the input ripple current. This results in much smaller RMS current in the input capacitor and reduction of input capacitors. Shutdown The converter can be shutdown by pulling the soft-start pin below 0.5V. This can be easily done by using an external small signal transistor. During shutdown the MOSFET drivers and the LDO controller turn off. Short-Circuit Protection The outputs are protected against the short circuit. The IRU3048 protects the circuit for shorted output by sensing the output voltages. The IRU3048 shuts down the PWM signals and LDO controller, when the output voltages drops below the set values. Under-Voltage Lockout The under-voltage lockout circuit assures that the MOSFET driver outputs and LDO controller remain in the off state whenever the supply voltages drop below set parameters. Normal operation resumes once the supply voltages rise above the set values.
APPLICATION INFORMATION
Design Example: The following example is a typical application for IRU3048 in current sharing mode. The schematic is Figure 9 on page 12. For Switcher VIN1 = 12V VOUT1 = 3.3V IOUT1 = 4A VIN2 = 5V VOUT2 = 1.8V IOUT2 = 4A DVOUT = 75mV fS = 200KHz PWM Section Output Voltage Programming Output voltage is programmed by reference voltage and external voltage divider. The Fb1 pin is the inverting input of the error amplifier, which is internally referenced to 1.25V. The divider is ratioed to provide 1.25V at the Fb1 pin when the output is at its desired value. The output voltage is defined by using the following equation: For Linear Regulator VIN3 = 3.3V VOUT3 = 2.5V IOUT3 = 2A VOUT1 = VREF3 1+
( R6) R8
---(1)
When an external resistor divider is connected to the output as shown in Figure 3.
VOUT1 IRU3048
Fb1 R8 R6
Figure 3 - Typical application of the IRU3048 for programming the output voltage. Equation (1) can be rewritten as: R6 = R8 3
( VOUT1 - 1) VREF
VOUT2=1.8V VREF=1.25V R15=1K, R14=442V
Will result to: VOUT1=3.3V VREF=1.25V R8=1K, R6=1.64K
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If the high value feedback resistors are used, the input bias current of the Fb pin could cause a slight increase in output voltage. The output voltage set point can be more accurate by using precision resistor. Soft-Start Programming The soft-start timing can be programmed by selecting the soft start capacitance value. The start up time of the converter can be calculated by using: Output Capacitor Selection The criteria to select the output capacitor is normally based on the value of the Effective Series Resistance (ESR). In general, the output capacitor must have low enough ESR to meet output ripple and load transient requirements, yet have high enough ESR to satisfy stability requirements. The ESR of the output capacitor is calculated by the following relationship: ESR [ DVO DIO ---(4)
tSTART = 75 3 Css (ms)
---(2)
Where: CSS is the soft-start capacitor (mF) For a start-up time of 7.5ms, the soft-start capacitor will be 0.1mF. Choose a ceramic capacitor at 0.1mF. Boost Supply Vc To drive the high-side switch it is necessary to supply a gate voltage at least 4V greater than the bus voltage. This is achieved by using a charge pump configuration as shown in Figure 9. The capacitor is charged up to approximately twice the bus voltage. A capacitor in the range of 0.1mF to 1mF is generally adequate for most applications. Input Capacitor selection The input filter capacitor should be based on how much ripple the supply can tolerate on the DC input line. The ripple current generated during the on time of control MOSFET should be provided by input capacitor. The RMS value of this ripple is expressed by: IRMS = IOUT D3(1-D) ---(3)
Where: DVO = Output Voltage Ripple DIO = Output Current DVO=75mV and DIO=3A, results to: ESR=25mV The Sanyo TPC series, PosCap capacitor is a good choice. The 6TPC150M 150mF, 6.3V has an ESR 40mV. Selecting two of these capacitors in parallel for each output, results to an ESR of 20mV which achieves our low ESR goal. The capacitor value must be high enough to absorb the inductor's ripple current. The larger the value of capacitor, the lower will be the output ripple voltage. The resulting output ripple current is smaller then each channel ripple current due to the 1808 phase shift. These currents cancel each other. The cancellation is not the maximum because of the different duty cycle for each channel. Inductor Selection The inductor is selected based on output power, operating frequency and efficiency requirements. Low inductor value causes large ripple current, resulting in the smaller size, but poor efficiency and high output noise. Generally, the selection of inductor value can be reduced to desired maximum ripple current in the inductor (i); the optimum point is usually found between 20% and 50% ripple of the output current. For the buck converter, the inductor value for desired operating ripple current can be determined using the following relation: Di 1 VOUT VIN - VOUT = L3 ; Dt = D3 ;D= Dt fS VIN VOUT L = (VIN - VOUT)3 ---(5) VIN3Di3fS Where: VIN = Max Input Voltage t = Turn On Time VOUT = Output Voltage D = Duty Cycle i = Inductor Ripple Current fS = Switching Frequency
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Where: D is the Duty Cycle, simply D=VOUT/VIN. IRMS is the RMS value of the input capacitor current. IOUT is the output current for each channel. For VIN1=12V, IOUT1=4A and D1=0.275 Results to: IRMS1=1.78A And for VIN2=5V, IOUT2=4A and D2=0.36 Results to: IRMS2 =1.92A For higher efficiency, a low ESR capacitor is recommended. For VIN1=12V, choose one Poscap from Sanyo 16TPB47M (16V, 47mF, 70mV, 1.4A) For VIN2=5V, choose one 6TPC150M (6.3V, 150mF, 40mV, 1.9A).
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For Di1=25% of I1, we get L1=9.9mH For Di2=25% of I2, we get: L2=5.7mH Panasonic provides a range of inductors in different values and low profile for large currents. For L1 choose ETQP6F102HFA (10.2mH, 4A) For L2 choose ELLATV6R8M (6.8mH, 4A) Power MOSFET Selection The selections criteria to meet power transfer requirements is based on maximum drain-source voltage (VDSS), gate-source drive voltage (VGS), maximum output current, On-resistance RDS(ON) and thermal management. The MOSFET must have a maximum operating voltage (VDSS) exceeding the maximum input voltage (VIN). The gate drive requirement is almost the same for both MOSFETs. Caution should be taken with devices at very low VGS to prevent undesired turn-on of the complementary MOSFET, which results a shoot-through current. The total power dissipation for MOSFETs includes conduction and switching losses. For the Buck converter the average inductor current is equal to the DC load current. The conduction loss is defined as: PCOND(Upper Switch) = ILOAD3RDS(ON)3D3q PCOND(Lower Switch) = ILOAD3RDS(ON)3(1 - D)3q q = RDS(ON) Temperature Dependency The total conduction loss is defined as:
PCON(TOTAL)=PCON(Upper Switch)q+PCON(Lower Switch)q
2 2
The total conduction losses for channel 1 is: PCON1 = 1.1W The total conduction losses for channel 2 is: PCON2 = 1.1W The control MOSFET contributes to the majority of the switching losses in synchronous Buck converter. The synchronous MOSFET turns on under zero-voltage condition, therefore the turn on losses for synchronous MOSFET can be neglected. With a linear approximation, the total switching loss can be expressed as: VDS(OFF) tr + tf 3 3 ILOAD ---(6) 2 T Where: VDS(OFF) = Drain to Source Voltage at off time tr = Rise Time PSW =
tf = Fall Time
T = Switching Period ILOAD = Load Current
VDS 90%
10% VGS td(ON) tr td(OFF) tf
Figure 4 - Switching time waveforms. From IRF7313 data sheet we obtain: IRF7313
The RDS(ON) temperature dependency should be considered for the worst case operation. This is typically given in the MOSFET data sheet. Ensure that the conduction losses and switching losses do not exceed the package ratings or violate the overall thermal budget. For this design, IRF7313 is a good choice. These devices provide low on-resistance in a compact SOIC 8Pin package. The MOSFETs have the following data: IRF7313 VDSS = 30V ID = 5.2A @ 708C RDS(ON) = 46mV @ VGS=4.5V q = 1.5 for 1508C (Junction Temperature)
tr = 13ns tf = 26ns
These values are taken under a certain condition test. For more detail please refer to the IRF7313 data sheet. By using equation (6), we can calculate the switching losses. PSW1 = 187.2mW PSW2 = 78mW
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IRU3048
Feedback Compensation The IRU3048 is a voltage mode controller; the control loop is a single voltage feedback path including error amplifier and error comparator. To achieve fast transient response and accurate output regulation, a compensation circuit is necessary. The goal of the compensation network is to provide a closed loop transfer function with the highest 0dB crossing frequency and adequate phase margin (greater than 458). The output LC filter introduces a double pole, -40dB/ decade gain slope above its corner resonant frequency, and a total phase lag of 1808 (see Figure 5). The Resonant frequency of the LC filter is expressed as follows: FLC = 1 2p Lo3Co ---(7)
VOUT R6 Fb
R8 VREF
Gain(dB)
E/A
Comp V e C18 R9
H(s) dB
FZ
Frequency
Figure 6 - Compensation network without local feedback and its asymptotic gain plot. The transfer function (Ve / VOUT) is given by: H(s) = gm 3
Figure 5 shows gain and phase of the LC filter. Since we already have 1808 phase shift just from the output filter, the system risks being unstable.
Gain 0dB -40dB/decade Phase 08
(
R8 1 + sR9C18 3 R6 + R8 sC18
)
---(9)
The (s) indicates that the transfer function varies as a function of frequency. This configuration introduces a gain and zero, expressed by: |H(s)| = gm 3 R8 3 R9 R6 3 R8 ---(11) ---(10)
FLC Frequency
-1808
FLC
Frequency
FZ =
1 2p 3 R9 3 C18
Figure 5 - Gain and phase of LC filter. The IRU3048's error amplifier is a differential-input transconductance amplifier. The output is available for DC gain control or AC phase compensation. The E/A can be compensated with or without the use of local feedback. When operated without local feedback the transconductance properties of the E/A become evident and can be used to cancel one of the output filter poles. This will be accomplished with a series RC circuit from Comp1 pin to ground as shown in Figure 6. The ESR zero of the LC filter expressed as follows: FESR = 1 2p 3 ESR 3 Co ---(8) The gain is determined by the voltage divider and E/A's transconductance gain. First select the desired zero-crossover frequency (Fo): FO1 > FESR and FO1 [ (1/5 ~ 1/10)3 fS Use the following equation to calculate R4: R9 = 1 VOSC FO13FESR1 R8 + R6 3 3 3 VIN1 FLC12 R8 gm ---(12)
Where: VIN1 = Maximum Input Voltage VOSC = Oscillator Ramp Voltage FO1 = Crossover Frequency for the master E/A FESR1 = Zero Frequency of the Output Capacitor FLC1 = Resonant Frequency of Output Filter gm = Error Amplifier Transconductance R8 and R6 = Resistor Dividers for Output Voltage Programming
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IRU3048
For: VIN1 = 12V VOSC = 1.25V FO1 = 30KHz FESR1 = 26.5KHz
ZIN VOUT C10 R8 R6 Fb R5 VREF
FLC1 = 2.8KHz R8 = 1K R6 = 1.64K gm = 600mmho
C12 R7 C11 Zf
This results to R9=46.4KV; Choose R9=46.4KV To cancel one of the LC filter poles, place the zero before the LC filter resonant frequency pole: FZ 75%FLC1 FZ 0.75 3 For: L3 = 10.2mH Co = 300mF Fz = 2.1KHz R9 = 46.4KV Using equations (11) and (13) to calculate C9, we get: C9 = 1630pF; Choose C9 = 1800pF Using equations (11),(12) and (13) for Ch2, where: VIN2 = 5V VOSC = 1.25V FO2 = 30KHz FESR2 = 26.5KHz FLC2 = 3.5KHz R15 = 1K R14 = 442V gm = 600mhmo 1 2p L3 3 CO ---(13)
Gain(dB)
E/A
V e Comp
H(s) dB
FZ1
FZ2
FP2
FP3
Frequency
Figure 7 - Compensation network with local feedback and its asymptotic gain plot. In such configuration, the transfer function is given by: 1Ve VOUT = 1 +
gmZf gmZIN
The error amplifier gain is independent of the transconductance under the following condition:
gmZf >> 1
and
gmZIN >>1
---(14)
We get: R11 = 38.9KV; Choose R11 = 39.2KV C19 = 1554pF; Choose C19 = 1800pF One more capacitor is sometimes added in parallel with C9 and R4. This introduces one more pole which is mainly used to supress the switching noise. The additional pole is given by: FP = 1 2p 3 R9 3 C18 3 CPOLE C18 + CPOLE
By replacing ZIN and Zf according to figure 7, the transformer function can be expressed as: H(s)= (1+sR7C11)3[1+sC10(R6+R8)] 3 C12C11 sR6(C12+C11) 1+sR7 3(1+sR8C10) C12+C11 1
[
(
)]
As known, transconductance amplifier has high impedance (current source) output, therefore, consider should be taken when loading the E/A output. It may exceed its source/sink output current capability, so that the amplifier will not be able to swing its output voltage over the necessary range. The compensation network has three poles and two zeros and they are expressed as follows: FP1 = 0 FP3 = 1 2p3R73 FZ1 = FP2 = 1 2p3R83C10 1 2p3R73C12
The pole sets to one half of switching frequency which results in the capacitor CPOLE: 1 1 CPOLE = p 3 R9 3 fS 1 p 3 R9 3 fS C18 fS For FP << 2 For a general solution for unconditionally stability for any type of output capacitors, in a wide range of ESR values we should implement local feedback with a compensation network. The typically used compensation network for voltage-mode controller is shown in Figure 7.
(C123C11) C12+C11
1 2p3R73C11
1 1 FZ2 = 2p3C103(R6 + R8) 2p3C103R6
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Cross Over Frequency: VIN 1 FO1 = R73C103 3 VOSC 2p3Lo3Co Where: VIN = Maximum Input Voltage VOSC = Oscillator Ramp Voltage Lo = Output Inductor Co = Total Output Capacitors The stability requirement will be satisfied by placing the poles and zeros of the compensation network according to following design rules. The consideration has been taken to satisfy condition 14 regarding transconductance error amplifier. 1) Select the crossover frequency: Fo < FESR and Fo [ (1/10 ~ 1/6)3 fS 2) Select R7, so that R7 >> 2 8) Use equation (1) to calculate R5: ---(15) R5 = VREF 3 R6 VOUT - VREF
These design rules will give a crossover frequency approximately one-tenth of the switching frequency. The higher the band width, the potentially faster the load transient speed. The gain margin will be large enough to provide high DC-regulation accuracy (typically -5dB to 12dB). The phase margin should be greater than 458 for overall stability. LDO Section Output Voltage Programming Output voltage for LDO is programmed by reference voltage and external voltage divider. The Fb3 pin is the inverting input of the error amplifier, which is internally referenced to 1.25V. The divider is ratioed to provide 1.25V at the Fb3 pin when the output is at its desired value. The output voltage is defined by using the following equation: RHIGH VOUT2 = VREF3 1+ RLOW
gm
3) Place first zero before LC's resonant frequency pole. FZ1 75% FLC 1 C11 = 2p 3 FZ1 3 R7 4) Place third pole at the half of the switching frequency. FP3 = C12 = fS 2 1 2p 3 R7 3 FP3
(
)
For: VOUT2 = 2.5V VREF = 1.25V RLOW = 1K Results to: RHIGH=1K LDO Power MOSFET Selection The first step in selecting the power MOSFET for the linear regulator is to select the maximum RDS(ON) based on the input to the dropout voltage and the maximum load current. RDS(ON) = VIN3 - VOUT2 IOUT2
C12 > 50pF If not, change R7 selection. 5) Place R7 in (15) and calculate C10: C10 [ 2p 3 Lo 3 FO 3 Co VOSC 3 R7 VIN
6) Place second pole at ESR zero. FP2 = FESR R8 = 1 2p 3 C10 3 FP2 1
For: VIN3 = 3.3V VOUT2 = 2.5V IOUT2 = 2A Results to: RDS(ON)(MAX) = 0.4V Note that since the MOSFET RDS(ON) increases with temperature, this number must be divided by ~1.5 in order to find the RDS(ON)(MAX) at room temperature. The IRLR2703 has a maximum of 0.065V RDS(ON) at room temperature, which meets our requirements.
Check if R8 >
gm
If R8 is too small, increase R7 and start from step 2. 7) Place second zero around the resonant frequency. FZ2 = FLC R6 = 1 - R8 2p 3 C10 3 FZ2
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Layout Consideration The layout is very important when designing high frequency switching converters. Layout will affect noise pickup and can cause a good design to perform with less than expected results. Start to place the power components, make all the connection in the top layer with wide, copper filled areas. The inductor, output capacitor and the MOSFET should be close to each other as possible. This helps to reduce the EMI radiated by the power traces due to the high switching currents through them. Place input capacitor directly to the drain of the high-side MOSFET, to reduce the ESR replace the single input capacitor with two parallel units. The feedback part of the system should be kept away from the inductor and other noise sources, and be placed close to the IC. In multilayer PCB use one layer as power ground plane and have a control circuit ground (analog ground), to which all signals are referenced. The goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function. These two grounds must be connected together on the PC board layout at a single point.
TYPICAL APPLICATION
12V to 3.3V @ 4A 12V to 1.8V @ 4A 3.3V to 2.5V @ 2A
12V
C2 33uF L1 1uH D1 BAT54S
C3 0.1uF
C1 1uF
VcH1 Vcc
C8 1uF
VcH2 HDrv1
C6 47uF 1/2 of Q2 IRF7313
C7 1uF
L3 10uH C10 470pF
C11, C12 2x 150uF
3.3V @ 4A
C13 1uF
3.3V
C9 47uF R2
VOUT3
Q1 IRLR2703 R5 10V
LDrv1 PGnd
1/2 of Q2 IRF7313
R4 4.7V R6 1.65K
2.5V @ 2A
1K C14 1uF C15 47uF R7 1K
Fb3
U1 Fb1 IRU3048
HDrv2
C16 47uF 1/2 of Q3 IRF7313
C17 1uF
R8 1K
C18 1800pF
R9
L4 6.8uH C20 470pF
Comp1
43.2K
C21, C22 2x 150uF
1.8V @ 4A
C23 1uF
C19 3900pF
R1 1
Comp2
16.2K
LDrv2
1/2 of Q3 IRF7313
R13 4.7V R14 442 V
SS
C24 0.1uF
Gnd
Fb2
R15 1K
Figure 8 - Typical application of IRU3048 in an on-board DC-DC converter using a single 12V supply for switcher.
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IRU3048
DEMO-BOARD APPLICATION
12V to 3.3V @ 4A 5V to 1.8V @ 4A 3.3V to 2.5V @ 2A
12V
C1 1uF C2 33uF L2 1uH
D1 BAT54S
L1
5V
C4 33uF
C3 0.1uF
1uH C5 1uF C6 47uF R1 1/2 of Q2 IRF7313 C7 1uF
VcH1 Vcc
C8 1uF
VcH2 HDrv1
2.15V R3
L4 10.2uH
C11, C12 2x 150uF
3.3V @ 4A
C13 1uF
3.3V
C9 47uF R2 Q1 IRLR2703 R5
LDrv1
2.15 V
1/2 of Q2 IRF7313
C10 470pF R4 4.7V
VOUT3
10V
PGnd Fb3
R6 1.65K
2.5V @ 2A
1K C14 1uF C15 47uF R7 1K
U1 Fb1 IRU3048
R10
C16 150uF 1/2 of Q3 IRF7313
C17 1uF
R8 1K
HDrv2
C18 1800pF R9 2.15V
L3 6.8uH C20 470pF R13 4.7V
Comp1
46.4K R12
C21, C22 2x 150uF
1.8V @ 4A
C23 1uF
LDrv2
C19 1800pF R11 2.15V
1/2 of Q3 IRF7313
Comp2
39.2K
SS
C24 0.1uF
R14 442V
Gnd
Fb2
R15 1K
Figure 9 - Demo-board application of IRU3048.
12
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Rev. 1.7 09/12/02
IRU3048
DEMO-BOARD APPLICATION
12V to 3.3V @ 4A 5V to 1.8V @ 4A 3.3V to 2.5V @ 2A Ref Desig Q1 Q2, Q3 U1 D1 L1, L2 L3 L4 C1,7,8,13, 14,17,23 C2, C4 C3, C24 C5 C9, C15 C10, C20 C18, C19 C6 C11,12,16 21,22 R1,3,10,12 R2 R4, R13 R5,7,8,15 R6 R9 R11 R14 Description MOSFET MOSFET Controller Diode Inductor Inductor Inductor Cap, Ceramic Cap, Tantalum Cap, Ceramic Cap, Ceramic Cap, Tantalum Cap, Ceramic Cap, Ceramic Cap, Poscap Cap, Poscap Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Value Qty Part# 30V, 45mV 1 IRLR2703 30V, 29mV, 5.2A 2 IRF7313 Synchronous PWM 1 IRU3048CF Fast Switching 1 BAT54S 1mH, 2.9A 2 ELL6SH1R0M 6.8mH, 4A 1 ELLATV6R8M 10.2mH, 4A 1 ETQP6F102HFA 1mF, Y5V, 16V 7 ECJ-2VF1C105Z 33mF, 16V 0.1mF, Y5V, 25V 1mF, X7R, 25V 47mF, 10V 470pF, X7R, 50V 1800pF, X7R, 50V 47mF, 16V, 70mV 150mF, 6.3V, 40mV 2.15V 10V 4.7V 1K, 1% 1.65K, 1% 46.4K 39.2K 442V, 1% 2 2 1 2 2 2 1 5 4 1 2 4 1 1 1 1 ECS-T1CD336R ECJ-2VF1E104Z ECJ-3YB1E105K ECS-T1AD476R ECJ-2VC1H471J ECJ-2VB1H182K 16TPB47M 6TPC150M Manuf Web site (www.) irf.com
IR IR IR IR Panasonic maco.panasonic.co.jp Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Sanyo sanyo.com/industrial Sanyo
Rev. 1.7 09/12/02
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13
IRU3048
WAVEFORMS
2A
2A
0A
0A
Figure 4 - Transient response @ IOUT = 0 to 2A for 3.3V output.
Figure 5 - Transient response @ IOUT = 0 to 2A for 1.8V output.
Figure 6 - Transient response @ IOUT = 0 to 2A for 2.5V output.
Figure 7 - Output voltage ripple for 3.3V @ 4A.
14
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Rev. 1.7 09/12/02
IRU3048
WAVEFORMS
Figure 8 - Output voltage ripple for 1.8V @ 4A.
Figure 9 - Gate signals for 3.3V output. Ch1: Output current 2A/div. Ch2: Gate signal for control FET 20V/div. Ch3: Gate signal for sync FET 10V/div.
VOUT1: 3.3V
VOUT2: 1.8V
VOUT3: 2.5V Vss
Figure 10 - Soft-start voltage Vs. output voltages.
Figure 11 - Gate signals for 1.8V output. Ch1: Output current 2A/div. Ch2: Gate signal for control FET 10V/div. Ch3: Gate signal for sync FET 10V/div.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information Data and specifications subject to change without notice. 02/01
Rev. 1.7 09/12/02
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15
IRU3048
(F) TSSOP Package 16-Pin
A L Q
R1 1.0 DIA B C R
E M O PIN NUMBER 1 F D DETAIL A P
N
G J
DETAIL A
H
K
SYMBOL DESIG A B C D E F G H J K L M N O P Q R R1
MIN 4.30 0.19
4.90 --0.85 0.05
08 0.50 0.09 0.09
16-PIN NOM 0.65 BSC 4.40 6.40 BSC --1.00 1.00 5.00 --0.90 --128 REF 128 REF --1.00 REF 0.60 0.20 -----
MAX 4.50 0.30
5.10 1.10 0.95 0.15
88 0.75 -----
NOTE: ALL MEASUREMENTS ARE IN MILLIMETERS.
16
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Rev. 1.7 09/12/02
IRU3048
(S) SOIC Package 16-Pin Surface Mount, Narrow Body
H A B C
E
DETAIL-A PIN NO. 1 D 0.386 0.015 x 458 T K F J
L
DETAIL-A
I
G
16-PIN SYMBOL A B C D E F G H I J K L T MIN MAX 9.80 9.98 1.27 BSC 0.51 REF 0.36 0.46 3.81 3.99 1.52 1.72 0.10 0.25 78 BSC 0.19 0.25 5.80 6.20 08 88 0.41 1.27 1.37 1.57
NOTE: ALL MEASUREMENTS ARE IN MILLIMETERS.
Rev. 1.7 09/12/02
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17
IRU3048
PACKAGE SHIPMENT METHOD
PKG DESIG F S PACKAGE DESCRIPTION TSSOP Plastic SOIC, Narrow Body PIN COUNT 16 16 PARTS PER TUBE --50 PARTS PER REEL 2500 2500 T&R Orientation Fig A Fig B
1
1
1
1
1
1
Feed Direction Figure A
Feed Direction Figure B
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information Data and specifications subject to change without notice. 02/01
18
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Rev. 1.7 09/12/02

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